EOSI1=0, ZCI=0, EOSI0=0, CIP0=0, CIP1=0, LLMTI=0, HLMTI=0
ADC Status Register
| UNDEFINED | This read-only bitfield is undefined and will always contain random data. |
| HLMTI | High Limit Interrupt 0 (0): No high limit interrupt request 1 (1): High limit exceeded, IRQ pending if CTRL1[HLMTIE] is set |
| LLMTI | Low Limit Interrupt 0 (0): No low limit interrupt request 1 (1): Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set |
| ZCI | Zero Crossing Interrupt 0 (0): No zero crossing interrupt request 1 (1): Zero crossing encountered, IRQ pending if CTRL1[ZCIE] is set |
| EOSI0 | End of Scan Interrupt 0 (0): A scan cycle has not been completed, no end of scan IRQ pending 1 (1): A scan cycle has been completed, end of scan IRQ pending |
| EOSI1 | End of Scan Interrupt 0 (0): A scan cycle has not been completed, no end of scan IRQ pending 1 (1): A scan cycle has been completed, end of scan IRQ pending |
| CIP1 | Conversion in Progress 0 (0): Idle state 1 (1): A scan cycle is in progress. The ADC will ignore all sync pulses or start commands |
| CIP0 | Conversion in Progress 0 (0): Idle state 1 (1): A scan cycle is in progress. The ADC will ignore all sync pulses or start commands |